A continuing trend in the field of electronic integrated circuits is to increase the density of circuit functions per semiconductor unit area, which reduces the cost and increases the performance and functionality of the integrated circuits. As is fundamental in this field, this increased density is obtained through reduction of the physical feature size of the circuit elements. A conventionally measured feature size in metal-oxide-semiconductor (MOS) integrated circuits is the minimum transistor gate width, or transistor channel length, with MOS transistors having channel lengths of less than one micron now commercially available.
For many manufacturers, dynamic random access memories (DRAMs) are the circuits which have the highest density and smallest feature size. This is due to the relatively high production rates and significant cost pressures for DRAMs, and also because much of the chip surface area of a DRAM is occupied by simple repetitive elements, namely one-transistor, one-capacitor memory cells.
However, the capacitance of a DRAM cell cannot be scaled at the same rate at which the other circuit feature sizes are scaled, beyond a certain point. This limitation is the well-known "soft error" mechanism by which DRAM cells lose data when impacted by alpha particles generated from cosmic rays, packaging material, and other sources. The soft error rate from alpha particles increases dramatically for DRAM cells that store less than about 2.5.times.10.sup.-13 coulombs of charge (approximately 50 fF at 5 volts). Since capacitance decreases with decreasing capacitor plate area, scaling the feature size of a DRAM cell, with constant capacitor dielectric and thickness, reduces the cell capacitance.
One way to maintain a constant capacitance with deceasing feature sizes is to reduce the dielectric thickness. Where silicon dioxide is the dielectric material, however, capacitor dielectrics thinner than about 10 nm are difficult to fabricate with acceptable manufacturing yield, as these films are particularly susceptible to pinholes and other point defects. Furthermore, ultrathin silicon dioxide films may not be able to withstand full power supply voltages placed thereacross; since the charge stored is equal to capacitance times voltage, a reduction in the applied voltage requires a further increase in the capacitance in order to store the same charge, exacerbating the problem.
Various techniques have been used to scale the size of DRAM devices while still maintaining sufficient capacitance and low soft error rates. For example, DRAMs are now available which have their cell capacitors located in trenches, taking advantage of the vertical dimension to provide larger capacitors occupying relatively little chip surface area.
Another common technique is to increase the dielectric constant of the capacitor dielectric from that of pure silicon dioxide, increasing the capacitance per unit area while decreasing the vulnerability of the film to defects. This can be accomplished by the use of composite, or multi-layer, capacitor dielectrics, such as films having both silicon nitride and silicon dioxide. Common configurations of these films include nitride-oxide (NO) and oxide-nitride-oxide (ONO) films. These composite films offer the yield advantage of relatively thick and reliable dielectrics while still providing high capacitance, due to the higher effective dielectric constant provided by silicon nitride.
A conventional method of forming NO and ONO films includes the deposition of silicon nitride over the silicon lower capacitor plate (in the case of the ONO film, over a thin thermal oxide layer), followed by the oxidation of an upper portion of the silicon nitride to form silicon dioxide (i.e., oxidized silicon nitride). The oxidized silicon nitride serves to "seal" (or repair) any pinholes in the deposited silicon nitride.
U.S. Pat. No. 4,623,912, issued Nov. 18, 1986, discloses a method of fabricating an oxide/nitride film by first thermally oxidizing silicon to form thermal silicon dioxide, followed by thermal nitridation of the silicon dioxide to form a silicon oxynitride film. The nitrogen concentration in this silicon oxynitride film has a decreasing concentration at depths away from the upper surface, so that the lower portion of the film is substantially silicon dioxide.
U.S. Pat. No. 4,621,277, issued Nov. 4, 1986, discloses a method of forming a nitride/oxide/nitride film using thermal processing. According to one disclosed embodiment, a silicon nitride film is first formed by the direct thermal nitridation of the underlying silicon. This silicon nitride film is then thermally oxidized to form thermal silicon dioxide at an upper portion; a portion of the thermal silicon dioxide is then thermally converted to a nitride. The resultant film is thus a composite film including varying amounts of oxide and nitride.
U.S. Pat. No. 4,882,649 discloses another method of forming a nitride/oxide/nitride film, in which a layer of silicon nitride is deposited over the underlying silicon. A layer of silicon dioxide is then either deposited over, or formed by thermal oxidation of a portion of, the first nitride layer. A layer of silicon nitride is then deposited over the silicon dioxide layer, completing the nitride/oxide/nitride film.
Each of these methods form the composite films by successive processing steps, either thermal reaction or deposition, thus building the film layer-by-layer. The processing flow for these films is thus relatively complex, requiring either that the wafers be moved between processing steps or alternatively requiring the use of relatively complex processing equipment capable of performing multiple processes in-situ. Particularly in the case where the wafers are transported after the formation of each layer, contamination of the surface of a layer can occur, resulting in increased charge trapping and other causes of failure at the interfaces between the layers of the film.
By way of further background, Josquin et al., "The Oxidation Inhibition in Nitrogen-Implanted Silicon", J. Electrochem. Soc.: SOLID-STATE SCIENCE AND TECHNOLOGY (August, 1982), pp. 1803-1810, describes the mechanism of oxidation inhibition in nitrogen-implanted silicon. As described in this article, an experiment was performed by which &lt;100&gt; single-crystal silicon with an overlying silicon dioxide layer (either native oxide of a thickness on the order of 2 nm, or a fabricated layer of a thickness on the order of 70 to 100 nm) was implanted with nitrogen ions. In particular, .sup.15 N.sub.2.sup.+ was implanted at a dose of 10.sup.16 /cm.sup.2 at an energy of 50 keV. This article further discloses that, after a one hour post-implant anneal at 1000.degree. C. in N.sub.2 atmosphere, the implanted nitrogen accumulates at the silicon-silicon dioxide interface (see FIGS. 3 and 7), creating a nitride-like layer thereat.
By way of further background, it is known to form single-crystal silicon-on-insulator (SOI) films by implanting oxygen ions and thereafter thermally treating the structure so that the implanted oxygen reacts with the silicon atoms thereat. In this conventional technique, commonly referred to as "SIMOX", the energy of the oxygen implant is selected so that a layer of silicon dioxide is formed at a certain depth into the body, so that a single-crystal layer of silicon remains over the oxide.
It is an object of the present invention to provide a method of forming a composite dielectric film including an oxide layer overlying a nitride layer, where the interface between the layers is not exposed during processing.
It is a further object of this invention to provide a method for forming such a film with reduced process complexity.
It is a further object of this invention to provide such a method where the nitride layer is in contact with the underlying silicon plate.
It is a further object of this invention to provide a capacitor, such as useful in a DRAM memory cell, formed according to such a method.
Other objects and advantages of the invention will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.